## 2 Answers

Isn’t the diagram incomplete? There should be an input at $T_1$, $T_2$ and $T_3$. If we assume there is a fxed input 1 one at these inputs then we may proceed as follow:

$T_0$ is always set, so $T_0$ toggles it’s output at every clock cycle.

$Q_0$ acts as the clock signal to next flip flop which is negative edge triggered, so $Q_1$ toggles when there is a $1\rightarrow0$ transition in $Q_0$.

Similarly, $Q_2$ and $Q_3$ toggle when there is a $1\rightarrow0$ transition in $Q_1$ and $Q_2$ respectively.

The state of all flip-flops are cleared when $Q_0^cQ_1^cQ_2^cQ_3^c$ is 1 i.e. at 0000 the state is set to 0000 again (basically doing nothing), this can be seen as there are two bubbles in clr line one from NAND and one from active low, so they cancel out.

$Q_0$ | $Q_1$ | $Q_2$ | $Q_3$ |
---|---|---|---|

0 | 0 | 0 | 0 |

1 | 0 | 0 | 0 |

0 | 1 | 0 | 0 |

1 | 1 | 0 | 0 |

0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 |

1 | 1 | 1 | 0 |

0 | 0 | 0 | 1 |

1 | 0 | 0 | 1 |

0 | 1 | 0 | 1 |

1 | 1 | 0 | 1 |

0 | 0 | 1 | 1 |

1 | 0 | 1 | 1 |

0 | 1 | 1 | 1 |

1 | 1 | 1 | 1 |

0 | 0 | 0 | 0 |

As we can see the arrangement is a MOD-16 counter as it resets back to 0000 after 15 states.

So the output frequency should be be $$\frac{70MHz}{16}=4.375MHz$$

But in this case an active low clear input is used when will clear the output of flip flops once a specific condition is met. Here the output of Q3,Q2’,Q1’,Q0’ are given to NAND gate. the bubble at NAND gate and an active low clear gate will remove each other. So the NAND gate can be replaced by AND gate with CLEAR input to Flip flop as active high. Therefore when Q3=1,Q2’=1 → (Q2=0), Q1’=1 → (Q1=0), Q0’=1 → (Q1=0) i.e states 0000 to 0111 will only be visible considering the counter as asynchronous. Hence it will work as mod 8 counter.

Therefore, output frequency = 70/8 = 8.75 MHz